VHDL MUX Test Bench Issue -

i'm trying learn vhdl through p. ashenden's book: designer's guide vhdl. chapter one's exercise 10 asks write 2-to-1 (i'm assuming 1 bit wide) mux in vhdl , simulate it. apologize in advance being complete noob. first vhdl code.

my mux didn't produce errors or warnings in synthesis. test bench doesn't produce errors or warnings, either. however, simulation comes blank, except names of signals.

i've tried looking @ multitude of other mux examples online (as bench test example book), of gave errors when tried sythesizing them, wasn't confident enough use them guides , didn't out of them. i'm not sure i'm doing wrong here. i'd include image of simulation, don't have enough rep points :(

also, realize mux should have cases when receives no select input/high impedance values, ect.. in case, i'm trying toy model working.

the mux code is:

library ieee; use ieee.std_logic_1164.all;  entity muxtop     port (a, b, sel: in bit;          z: out bit); end muxtop;  architecture behav of muxtop begin     choose: process     begin         if sel = '0'             z <= b;         else             z <= a;         end if;     end process choose; end architecture behav; 

the test bench code is:

library ieee; use ieee.std_logic_1164.all;  entity muxtest end muxtest;  architecture behavior of muxtest   -- component declaration unit under test (uut)      component muxtop     port(         : in  bit;         b : in  bit;         sel : in  bit;         z : out  bit         );     end component muxtop;      --inputs    signal : bit := '0';    signal b : bit := '0';    signal sel : bit := '0';     --outputs    signal z : bit;  begin  -- instantiate unit under test (uut)     uut: muxtop port map (            => a,            b => b,            sel => sel,            z => z            );     -- stimulus process    stimulus: process    begin        wait 10 ns;        <= '1';        wait 10 ns;        sel <= '1';        wait 10 ns;        b <= '1';        wait;    end process stimulus; end architecture behavior; 

you don't need use clause package std_logic_1164 when using type bit (declared in package standard).

your process statement choose in muxtop has no sensitivity clause cause process continually execute in simulation. (it won't until trip on delta cycle iteration limit might set infinity).

i added sensitivity list, commented out superfluous use clauses in 2 design units , added more stimulus steps final wait 10 ns; allow last action seen in testbench:

library ieee; -- use ieee.std_logic_1164.all;  entity muxtop     port (a, b, sel: in bit;          z: out bit); end muxtop;  architecture behav of muxtop begin     choose: process (a, b, sel)  --     begin         if sel = '0'             z <= b;         else             z <= a;         end if;     end process choose; end architecture behav;  library ieee; -- use ieee.std_logic_1164.all;  entity muxtest end muxtest;  architecture behavior of muxtest   -- component declaration unit under test (uut)      component muxtop     port(         : in  bit;         b : in  bit;         sel : in  bit;         z : out  bit         );     end component muxtop;      --inputs    signal : bit := '0';    signal b : bit := '0';    signal sel : bit := '0';     --outputs    signal z : bit;  begin  -- instantiate unit under test (uut)     uut: muxtop port map (            => a,            b => b,            sel => sel,            z => z            );     -- stimulus process    stimulus: process    begin        wait 10 ns;        <= '1';        wait 10 ns;        sel <= '1';        wait 10 ns;        sel <= '0';     -- added        wait 10 ns; -- added        b <= '1';        wait 10 ns; -- added        wait;    end process stimulus; end architecture behavior; 

and gives:

(clickable)